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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Bit Name
Mnemonic
S7:0
Slave IRs
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-14. ICW3 Register — Master Cascade Configuration
Initialization Command Word 3 (Master)
ICW3 (accessed through MPICP1)
Selects cascaded input pins on master 8259A.
S
S
7
6
Reset
State
XXH
Each S7:0 bit corresponds to the IR line of the
same number. Setting an S7:0 bit indicates that
a slave 8259A is attached to the corresponding
IR line.
NOTE: The S7 bit must be set in the master
8259A module for the 80C186EC/C188EC.
INTERRUPT CONTROL UNIT
S
S
S
S
S
5
4
3
2
1
Function
0
S
0
A1222-0A
8-27
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