The Two-Channel Dma Module - Intel 80C188EC User Manual

The Chip-Select Unit monitors the BIU addresses to determine which chip-select, if any, to acti-
vate. Because the DMA Unit uses the BIU, chip-selects are active for DMA cycles. If a DMA
channel accesses a region of memory or I/O space within a chip-select's programmed range, then
that chip-select is asserted during the cycle. The Chip-Select Unit will not recognize DMA cycles
that access I/O space above 64K.

10.1.10 The Two-Channel DMA Module

Two DMA channels are combined with arbitration logic to form a DMA module (see Figure
10-5).
10.1.10.1 DMA Channel Arbitration
Within a two-channel DMA module, the arbitration logic decides which channel takes prece-
dence when both channels simultaneously request transfers. Each channel can be set to either low
priority or high priority. If the two channels are set to the same priority (either both high or both
low), then the channels rotate priority.
10.1.10.1.1 Fixed Priority
Fixed priority results when one channel in a module is programmed to high priority and the other
is set to low priority. If both DMA requests occur simultaneously, the high priority channel per-
forms its transfer (or transfers) first. The high priority channel continues to perform transfers as
long as the following conditions are met:
•
the channel's DMA request is still active
•
the channel has not terminated or suspended transfers (through programming or interrupts)
•
the channel has not released the bus (through the insertion of idle states for destination-
synchronized transfers)
The last point is extremely important when the two channels use different synchronization. For
example, consider the case in which channel 1 is programmed for high priority and destination
synchronization and channel 0 is programmed for low priority and source synchronization. If a
DMA request occurs for both channels simultaneously, channel 1 performs the first transfer. At
the end of channel 1's deposit cycle, two idle states are inserted (thus releasing the bus). With the
bus released, channel 0 is free to perform its transfer even though the higher-priority channel
has not completed all of its transfers. Channel 1 regains the bus at the end of channel 0's trans-
fer. The transfers will alternate as long as both requests remain active.
DIRECT MEMORY ACCESS UNIT
10-9