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BUS INTERFACE UNIT
CLKOUT
S2:0
ALE
A19:16
BHE
[A15:8]
AD15:0
[AD7:0]
WR
DT/R
DEN
Status Bits
S2
S1
S0
0
1
0
1
1
0
Figure 3-22 illustrates a typical 16-bit interface connection to a read/write device. Write bus cy-
cles have many parameters that must be evaluated in determining the compatibility of a memory
(or I/O) device. Table 3-5 lists some critical write bus cycle parameters.
3-24
T1
Status Valid
Address Valid
Address
Valid
Figure 3-21. Typical Write Bus Cycle
Table 3-4. Write Bus Cycle Types
Write I/O — Initiated by executing IN, OUT, INS, OUTS instructions or by the
DMA Unit. A15:0 select the desired I/O port. A19:16 are driven to zero (see
Chapter 10, "Direct Memory Access Unit").
Write Memory — Initiated by any of the Byte/ Word memory instructions or the
DMA Unit. A19:0 selects the desired byte or word memory location.
T2
T3
A18:16 = 0, A19=Valid Status
Valid
Data Valid
Bus Cycle Type
T4
A1085-0A
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