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CHIP-SELECT UNIT
Register Name:
Register Mnemonic:
Register Function:
15
C
C
C
S
S
S
9
8
7
Bit
Mnemonic
CS9:0
Stop
Address
CSEN
Chip-Select
Enable
ISTOP
Ignore Stop
Address
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. The reset state of
CSEN and ISTOP is '1' for the UCSSP register.
6-8
Chip-Select Stop Register
UCSSP, LCSSP, GCSxSP (x=0-7)
Defines chip-select stop address and other control
functions.
C
C
C
C
C
S
S
S
S
S
6
5
4
3
2
Reset
Bit Name
State
3FFH
0
(Note)
0
(Note)
Figure 6-6. STOP Register Definition
C
C
S
S
1
0
Function
Defines the ending address for the chip-select.
CS9:0 are compared with the A19:10 (memory
bus cycles) or A15:6 (I/O bus cycles) address
bits. A less than result enables the chip-select.
CS9:0 are ignored if ISTOP is set.
Disables the chip-select when cleared. Setting
CSEN enables the chip-select.
Setting this bit disables stop address checking,
which automatically sets the ending address at
0FFFFFH (memory) or 0FFFFH (I/O). When
ISTOP is cleared, the stop address require-
ments must be met to enable the chip-select.
0
C
I
M
R
S
S
E
D
E
T
M
Y
N
O
P
A1164-0A
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