Intel 80C188EC User Manual page 106

Figure 3-20 illustrates a typical 16-bit interface connection to a read-only device interface. The
same example applies to an 8-bit bus system, except that no devices connect to an upper bus. Four
parameters (Table 3-3) must be evaluated when determining the compatibility of a memory (or
I/O) device. T defines the delay through the address latch.
ADLTCH
Table 3-3. Read Cycle Critical Timing Parameters
Memory Device
Parameter
T
OE
T
ACC
T
CE
T
DF
T , T and T define the maximum data access requirements for the memory device. These
OE ACC CE
device parameters must be less than the value calculated in the equation column. An equal to or
greater than result indicates that wait states must be inserted into the bus cycle.
T determines the maximum time the memory device can float its outputs before the next bus
DF
cycle begins. A T value greater than the equation result indicates a buffer fight. A buffer fight
DF
means two (or more) devices are driving the bus at the same time. This can lead to short circuit
conditions, resulting in large current spikes and possible device damage.
T cannot be lengthened (other than by slowing the clock rate). To resolve a buffer fight con-
RHAX
dition, choose a faster device or buffer the AD bus (see "Buffering the Data Bus" on page 3-37).
Description
Output enable (RD low) to data valid
Address valid to data valid
Chip enable (UCS) to data valid
Output disable (RD high) to output float
BUS INTERFACE UNIT
Equation
2T – T – T
2
CLOV CLIS
3T – T –T T
–
2
CLOV ADLTCH CLIS
3T – T – T
2
CLOV CLIS
T
RHAX
3-21