Refresh Interval Counter Pal; Refresh Address Counter Pal - Intel 80386 Reference Manual

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TABLE OF CONTENTS
Title
Shared Bus Interface ............................................................................ ..
80386-MUl TIBUS® I Interface ............................................................. ..
MUl TIBUS® I Address latches and Data Transceivers ....................... ..
Wait-State Generator logic .................................................................. ..
MUl TIBUS® Arbiter and Bus Controller ............................................... ..
MUl TIBUS® I Read Cycle Timing ......................................................... .
MUl TIBUS® I Write Cycle Timing ......................................................... .
Bus Priority Resolution ..................... : .................................................... .
Operating Mode Configurations ............................................................. .
Bus-Select logic for Interrupt Acknowledge ........................................ ..
Byte-Swapping logic ............................................................................ .
Bus-Timeout Protection Circuit .............................................................. .
ilBX™ Signal Generation ....................................................................... .
iPSB Bus Cycle Timing .......................................................................... .
iPSB Bus Interface ................................................................................ .
Reducing Characteristic Impedance ...................................................... .
Circuit without Decoupling ..................................................................... .
Decoupling Chip Capacitors .................................................................. .
Decoupling leaded Capacitors .............................................................. .
Series Termination ................................................................................. .
Split Termination ........ , ........................................................................... .
Avoid Closed-loop Signal Paths .......................................................... ..
ClK2 Series Termination ....................................................................... .
ClK2 loading ........................................................................................ .
ClK2 Waveforms .................................................................................. .
4-Byte Diagnostic Program ................................................................... ..
More Complex Diagnostic Program ....................................................... .
Object Code for Diagnostic Program ..................................................... .
80386 Self-Test ..................................................................................... .
TlB Test Registers .............................................................................. ..
PAl-1 State Listings .............................................................................. ..
PAl-2 State Listings .............................................................................. .
PAl-1 Equations .................................................................................... .
PAl-2 Equations .................................................................................... .
80387 Emulator PAL Equations ........................................................... ..
PAL Sampling Edges ............................................................................. .
3-ClK DRAM State PAL Equations ...................................................... ..
2-ClK DRAM State PAL Equations ....................................................... .
3-ClK DRAM Control PAL Equations ................................................... .
2-ClK DRAM Control PAL Equations .................................................. ..
Refresh Interval Counter PAL Equations .............................................. ..
Refresh Address Counter PAL Equations ............................................ ..
DRAM Circuit Timing Diagram ............................................. : ................ ..
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