Table of Contents
Advertisement
BUS INTERFACE UNIT
After several TI bus states, all address/data, address/status and bus control pins drive to a known
state when Powerdown or Idle Mode is enabled. The address/data and address/status bus pins
force a low (0) state. Bus control pins force their inactive state. Figure 3-3 lists the state of each
pin after entering the HALT bus state.
AD15:0 (AD7:0 for 8-bit)
A15:8 (8-bit)
A19:16
BHE (16-bit)
RD, WR, DEN, DT/R, RFSH (8-bit), S2:0
3-30
Table 3-6. HALT Bus Cycle Pin States
Pin(s)
Pin State
No Powerdown
Powerdown
or Idle Mode
or Idle Mode
Float
Drive Zero
Drive Address
Drive Zero
Drive 8H or Zero
Drive Zero
Drive Last Value
Drive One
Drive One
Drive One
Advertisement
Table of Contents
