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Intel 80C186EC Manual

16-bit high-integration embedded processors
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80C186EC 80C188EC AND 80L186EC 80L188EC
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Integrated Feature Set
Y
Low-Power Static Enhanced 8086
CPU Core
Two Independent DMA Supported
UARTs each with an Integral Baud
Rate Generator
Four Independent DMA Channels
22 Multiplexed I O Port Pins
Two 8259A Compatible
Programmable Interrupt Controllers
Three Programmable 16-Bit Timer
Counters
32-Bit Watchdog Timer
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
Power Management Unit
On-Chip Oscillator
System Level Testing Support
(ONCE Mode)
Direct Addressing Capability to 1 Mbyte
Y
Memory and 64 Kbyte I O
Low-Power Operating Modes
Y
Idle Mode Freezes CPU Clocks but
Keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Powersave Mode Divides All Clocks
by Programmable Prescalar
The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family
incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088
The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common
system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic
silicon die
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT © INTEL CORPORATION, 2004
X
Fully Static Operation
X
True CMOS Inputs and Outputs
Y
Y
Y
Y
Y
August, 2004
Available in Extended Temperature
Range (
40 C to
85 C)
b
a
Supports 80C187 Numerics Processor
Extension (80C186EC only)
Package Types
100-Pin EIAJ Quad Flat Pack (QFP)
100-Pin Plastic Quad Flat Pack
(PQFP)
100-Pin Shrink Quad Flat Pack
(SQFP)
Speed Versions Available (5V)
25 MHz (80C186EC25 80C188EC25)
20 MHz (80C186EC20 80C188EC20)
13 MHz (80C186EC13 80C188EC13)
Speed Version Available (3V)
16 MHz (80L186EC16 80L188EC16)
13 MHz (80L186EC13 80L188EC13)
Order Number: 272434-006

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  • Page 1 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT ©...

  • Page 2: Table Of Contents

    80C186EC 80C188EC and 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR CONTENTS CONTENTS PAGE PAGE Recommended Connections INTRODUCTION DC SPECIFICATIONS 80C186EC CORE ARCHITECTURE versus Frequency and Voltage Bus Interface Unit PDTMR Pin Delay Calculation Clock Generator AC SPECIFICATIONS 80C186EC PERIPHERAL AC Characteristics 80C186EC25...
  • Page 3 80C186EC 188EC 80L186EC 188EC 272434 –1 NOTE Pin names in parentheses apply to the 80C188EC 80L188EC Figure 1 80C186EC 80L186EC Block Diagram...

  • Page 4: Introduction

    The 80C186EC provides an on-chip clock generator 80C186EC for both internal and external clock generation The clock generator features a crystal oscillator a divide- The future set of the 80C186EC meets the needs of by-two counter and three low-power operating low-power space-critical applications Low-power modes...

  • Page 5: 80C186Ec Peripheral Architecture

    80C186EC PERIPHERAL ARCHITECTURE 32-bit Watchdog Timer Unit I O Port Unit The 80C186EC integrates several common system Refresh Control Unit peripherals with a CPU core to create a compact yet powerful system The integrated peripherals are de- Power Management Unit...
  • Page 6 80C186EC 188EC 80L186EC 188EC Function Function Function Function Offset Offset Offset Offset Master PIC Port 0 T2 Count GCS0 Start DMA 0 Source Low Master PIC Port 1 T2 Compare GCS0 Stop DMA 0 Source High Slave PIC Port 0...

  • Page 7: Programmable Interrupt Controllers

    The third timer is not connected to any external pins and can only be The I O Port Unit on the 80C186EC supports two clocked internally However it can be used to clock 8-bit channels and one 6-bit channel of input output...

  • Page 8: Power Management Unit

    To facilitate testing and inspection of devices when reset. this reason fixed into a target system, the 80C186EC has a test A19/S6/ONCE is classified as an input/ mode available which forces all output and input/ output pin. output pins to be placed in the high-impedance Column 3.
  • Page 9 80C186EC 188EC 80L186EC 188EC Column 4 Output States (for O and I O types the processor is in the Hold Acknowledge state only) R(Z) indicates that these pins will float while RESIN is low P(0) and I(0) indicate that these pins will drive...
  • Page 10 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions Input Output Pin Name Pin Description Type Type States POWER 10% power supply connection GROUND CLKIN A(E) CLocK INput is the external clock input An external oscillator operating at two times the required processor...
  • Page 11 These pins drive address information during the address phase of the bus cycle During T2 and T3 these pins drive A17 S4 R(WH) status information (which is always 0 on the 80C186EC) A16 S3 I(0) These pins are used as inputs during factory test driving...
  • Page 12 I(1) P(1) READY A(L) READY input to signal the completion of a bus cycle READY must be active to terminate any 80C186EC bus cycle unless S(L) it is ignored by correctly programming the Chip-Select unit (Note 1) H(Z) Data ENable output to control the enable of bi-directional...
  • Page 13 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions (Continued) Input Output Pin Name Pin Description Type Type States PEREQ A(L) Processor Extension REQuest signals that a data transfer between an 80C187 Numerics Processor Extension and Memory is pending Systems not using an...
  • Page 14 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions (Continued) Input Output Pin Name Pin Description Type Type States P3 1 TXI1 H(X) H(Q) Transmit Interrupt output goes active to indicate that serial channel 1 has completed a transfer TXI1 is...

  • Page 15: Pinout

    80C186EC 188EC 80L186EC 188EC from the top side of the component (i e contacts Pinout facing down) Tables 3 and 4 list the pin names with package loca- Tables 7 and 8 list the pin names with package loca- tion for the 100-pin Plastic Quad Flat Pack (PQFP)
  • Page 16 80C186EC 188EC 80L186EC 188EC Table 4 PQFP Pin Locations with Pin Name Name Name Name Name DRQ3 DMAI0 P3 2 BHE (RFSH) A17 S4 T0OUT DMAI1 P3 3 A16 S3 T0IN P3 4 AD15 (A15) T1OUT P3 5 AD14 (A14)
  • Page 17 80C186EC/188EC, 80L186EC/188EC 272434– 3 NOTE: This is the FPO number location (indicated by X’s). Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP)
  • Page 18 80C186EC 188EC 80L186EC 188EC Table 5 QFP Pin Names with Package Location AD Bus Bus Control Processor Control Name Name Name Name RESIN BHE (RFSH) RESOUT CLKIN OSCOUT P1 7 GCS7 CLKOUT P1 6 GCS6 TEST BUSY P1 5 GCS5...
  • Page 19 80C186EC 188EC 80L186EC 188EC Table 6 QFP Package Location with Pin Names Name Name Name Name DRQ0 P2 7 CTS1 LOCK DRQ1 P3 0 RXI1 A19 S6 ONCE DRQ2 P3 1 TXI1 A18 S5 DRQ3 DMAI0 P3 2 BHE (RFSH)
  • Page 20 80C186EC/188EC, 80L186EC/188EC 272434– 4 NOTE: This is the FPO number location (indicated by X’s). Figure 5: Quad Flat Pack (EIAJ) Pinout Diagram...
  • Page 21 80C186EC 188EC 80L186EC 188EC Table 7 SQFP Pin Functions with Location AD Bus Bus Control Processor Control RESIN BHE (RFSH) RESOUT CLKIN OSCOUT P1 0 GCS0 CLKOUT P1 1 GCS1 TEST BUSY P1 2 GCS2 P1 3 GCS3 READY INT0...
  • Page 22 80C186EC 188EC 80L186EC 188EC Table 8 SQFP Pin Locations with Pin Names Name Name Name Name DRQ3 P3 2 DMAI0 BHE (RFSH) T0OUT P3 3 DMAI1 T0IN P3 4 AD15 (A15) T1OUT P3 5 AD14 (A14) T1IN INT0 AD13 (A13)
  • Page 23 80C186EC/188EC, 80L186EC/188EC 272434– 5 NOTE: This is the FPO number location (indicated by X’s) Figure 6: 100-Pin Shrink Quad Flat Pack Package (SQFP)

  • Page 24: Package Thermal Specifications

    (the ambient temperature) can be calculated Package Thermal Specifications from i (thermal resistance from the case to ambi- ent) with the following equation The 80C186EC 80L186EC is specified for operation when T (the case temperature) is within the range 40 C to 100 C T...

  • Page 25: Electrical Specifications

    The specifica- tions are subject to change without notice Verify with Absolute Maximum Ratings your local Intel Sales office that you have the latest data sheet before finalizing a design Storage Temperature 65 C to 150 C WARNING Stressing the device beyond the ‘‘Absolute...

  • Page 26: Dc Specifications

    80C186EC 188EC 80L186EC 188EC DC SPECIFICATIONS (80C186EC 80C188EC) Symbol Parameter Units Notes Supply Voltage Input Low Voltage 0 3 V Input High Voltage 0 7 V Output Low Voltage 0 45 3 mA (Min) Output High Voltage 2 mA (Min)
  • Page 27 80C186EC 188EC 80L186EC 188EC DC SPECIFICATIONS (80L186EC13 80L188EC13) Symbol Parameter Units Notes Supply Voltage Input Low Voltage 0 3 V Input High Voltage 0 7 V Output Low Voltage 0 45 3 mA (Min) Output High Voltage 2 mA (Min)
  • Page 28 80C186EC 188EC 80L186EC 188EC DC SPECIFICATIONS (80L186EC16 80L188EC16) (Operating Temperature 0 C to 70 C) Symbol Parameter Units Notes Supply Voltage Input Low Voltage 0 3 V Input High Voltage 0 7 V Output Low Voltage 0 45 3 mA (Min)

  • Page 29: Icc Versus Frequency And Voltage

    Operating Frequency desired delay in seconds capacitive load on PDTMR in microfarads Measuring C on a device like the 80C186EC would be difficult Instead C is calculated using Example For a delay of 300 ms a capacitor value of the above formula with I...

  • Page 30: Ac Specifications

    80C186EC 188EC 80L186EC 188EC AC SPECIFICATIONS AC Characteristics 80C186EC25 25 MHz Symbol Parameter Units Notes INPUT CLOCK CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period...

  • Page 31: Ac Characteristics 80C186Ec20

    80C186EC 188EC 80L186EC 188EC AC SPECIFICATIONS AC Characteristics 80C186EC25 (Continued) 25 MHz Symbol Parameter Units Notes SYNCHRONOUS INPUTS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 CHIS P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0...
  • Page 32 80C186EC 188EC 80L186EC 188EC AC SPECIFICATIONS AC Characteristics 80C186EC-20 80C186EC-13 Symbol Parameter Unit Notes INPUT CLOCK 20 MHz 13 MHz CLKIN Frequency CLKIN Period 38 5 CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK...

  • Page 33: Ac Characteristics 80L186Ec13

    80C186EC 188EC 80L186EC 188EC AC Characteristics 80L186EC13 Symbol Parameter Unit Notes INPUT CLOCK 13 MHz CLKIN Frequency CLKIN Period 38 5 CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period...

  • Page 34: Ac Characteristics 80L186Ec16

    80C186EC 188EC 80L186EC 188EC AC Characteristics 80L186EC13 (Continued) NOTES 6 See Figure 15 for rise and fall times applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release CHOV1 applies to RD and WR only after a HOLD release...

  • Page 35: Relative Timings

    RD and WR only after a HOLD release CHOV2 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation Relative Timings (80C186EC-25 20 13 80L186EC-16 13) Symbol Parameter Unit Notes...

  • Page 36: Serial Port Mode 0 Timings

    8259A IRES modules 4 See INTA Cycle Waveforms for definition 5 To guarantee interrupt is not spurious Serial Port Mode 0 Timings (80C186EC-25 20 13 80L186EC-16 13) Symbol Parameter Unit Notes RELATIVE TIMINGS...

  • Page 37: Ac Test Conditions

    80C186EC 188EC 80L186EC 188EC AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance 272434 –6 50 pF for all signals...
  • Page 38 80C186EC 188EC 80L186EC 188EC 272434 –8 Figure 9 Output Delay and Float Waveforms 272434 –9 Figure 10 Input Setup and Hold 272434–10 Figure 11 Relative Interrupt Signal Timings...
  • Page 39 80C186EC 188EC 80L186EC 188EC 272434 –11 Figure 12 Relative Signal Waveform 272434 –12 Figure 13 Serial Port Mode 0 Waveform...

  • Page 40: Derating Curves

    80C186EC 188EC 80L186EC 188EC DERATING CURVES 272434–13 Figure 14 Typical Output Delay Variations versus Load Capacitance 272434–14 Figure 15 Typical Rise and Fall Variations versus Load Capacitance rectly using a RC reset circuit but the designer must RESET ensure that the ramp time for V...
  • Page 41 80C186EC 188EC 80L186EC 188EC Figure 16 Cold RESET Waveforms...
  • Page 42 80C186EC 188EC 80L186EC 188EC Figure 17 Warm RESET Waveforms...

  • Page 43: Bus Cycle Waveforms

    80C186EC 188EC 80L186EC 188EC bus signals to CLKOUT These figures along with BUS CYCLE WAVEFORMS the information present in AC Specifications allow the user to determine all the critical timing analysis Figures 18 through 24 present the various bus cy-...
  • Page 44 80C186EC 188EC 80L186EC 188EC 272434 –18 Pin names in parentheses apply to 80C188EC 80L188EC Figure 19 Memory Write and I O Write Cycle Waveforms...
  • Page 45 80C186EC 188EC 80L186EC 188EC 272434 –19 NOTES 1 Address information is invalid If previous bus cycle was a read then the AD15 0 (AD7 0) lines will float during T1 Otherwise the AD15 0 (AD7 0) lines will continue to drive during T1 (data is invalid) All other control lines are in their...
  • Page 46 80C186EC 188EC 80L186EC 188EC 272434 –20 Pin names in parentheses apply to 80C188EC 80L188EC Figure 21 Interrupt Acknowledge Cycle Waveforms...
  • Page 47 80C186EC 188EC 80L186EC 188EC 272434 –21 Pin names in parentheses apply to 80C188EC 80L188EC Figure 22 HOLD HLDA Cycle Waveforms...
  • Page 48 80C186EC 188EC 80L186EC 188EC 272434 –22 Pin names in parentheses apply to 80C188EC 80L188EC Figure 23 Refresh during HLDA Waveforms...
  • Page 49 80C186EC 188EC 80L186EC 188EC 272434 –23 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EC 80L188EC Figure 24 READY Cycle Waveforms...

  • Page 50: Execution Timings

    With a 16-bit BIU the 80C186EC has sufficient bus cycles necessary to execute instructions The fol- performance to ensure that an adequate number of...

  • Page 51: Instruction Set Summary

    80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY 80C186EC 80C188EC Function Format Comments Clock Clock Cycles Cycles DATA TRANSFER Move Register to Register Memory 1 0 0 0 1 0 0 w mod reg r m 2 12 2 12 Register memory to register...
  • Page 52 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) 80C186EC 80C188EC Function Format Comments Clock Clock Cycles Cycles DATA TRANSFER (Continued) SEGMENT Segment Override 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0...
  • Page 53 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) 80C186EC 80C188EC Function Format Comments Clock Clock Cycles Cycles ARITHMETIC (Continued) IMUL Integer multiply (signed) 1 1 1 1 0 1 1 w mod 1 0 1 r m Register-Byte 25–28 25–28 Register-Word 34–37...
  • Page 54 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) 80C186EC 80C188EC Function Format Comments Clock Clock Cycles Cycles LOGIC (Continued) Exclusive or Reg memory and register to either 0 0 1 1 0 0 d w mod reg r m 3 10...
  • Page 55 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) 80C186EC 80C188EC Function Format Comments Clock Clock Cycles Cycles CONTROL TRANSFER (Continued) Return from CALL Within segment 1 1 0 0 0 0 1 1 Within seg adding immed to SP 1 1 0 0 0 0 1 0...
  • Page 56 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) 80C186EC 80C188EC Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL Clear carry 1 1 1 1 1 0 0 0 Complement carry 1 1 1 1 0 1 0 1 Set carry...

  • Page 57: Errata

    80C186EC 188EC 80L186EC 188EC ERRATA REVISION HISTORY An 80C186EC 80L186EC with a STEPID value of This data sheet replaces the following data sheets 0002H has no known errata A device with a STEPID 272072-003 80C186EC of 0002H can be visually identified by noting the...

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