Intel 80C188EC User Manual page 233

INTERRUPT CONTROL UNIT
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
LTIM Level
Trigger
Mode
SNGL Single
8259A in
System
IC4 ICW4
Needed?
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
The LTIM bit controls the edge detection circuitry on the interrupt request input lines. There is
no provision for setting the mode of the individual IR lines.
The SNGL bit selects either single master or cascade (master/slave) mode. The SNGL bit must
be cleared to select cascade mode for both 8259A modules in the 80C186EC/C188EC Interrupt
Control Unit.
The IC4 bit, when set, informs the 8259A module that an ICW4 command will be issued. ICW4
is always needed for the 80C186EC/C188EC. The remaining bits in the ICW1 register must be
programmed with the bit values specified in Figure 8-12.
8-24
Initialization Command Word 1
ICW1 (accessed through MPICP0 and SPICP0)
Begins 8259A module initialization sequence.
Reset
Bit Name
State
X
X
X
Figure 8-12. ICW1 Register
0 0 0 1
M
Function
Set to select level triggering on IR inputs. Clear
to select edge triggering.
Set when 8259A module is the only one in
system. Clear to select cascade mode.
NOTE: SNGL must always be cleared for
80C186EC and 80C188EC systems.
Set to indicate that an ICW4 is needed.
NOTE: IC4 must always be set for 80C186EC
and 80C188EC systems.
0
L S I
T N C
I 0 G 4
L
A1220-0A