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8.3.3.1
Default (Fixed) Priority ...................................................................................8-11
8.3.3.2
Changing the Default Priority: Specific Rotation ............................................8-11
8.3.3.3
Changing the Default Priority: Automatic Rotation ........................................8-12
8.3.4
The In-Service Register ..........................................................................................8-12
8.3.4.1
Clearing the In-Service Bits: Non-Specific End-Of-Interrupt ..........................8-13
8.3.4.2
Clearing the In-Service Bits: Specific End-Of-Interrupt .................................8-13
8.3.4.3
Automatic End-Of-Interrupt Mode .................................................................8-13
8.3.5
Masking Interrupts ..................................................................................................8-14
8.3.6
Cascading 8259As ..................................................................................................8-14
8.3.6.1
Master/Slave Connection ..............................................................................8-14
8.3.6.2
The Cascaded Interrupt Acknowledge Cycle: An Example ...........................8-16
8.3.6.3
Master Cascade Configuration ......................................................................8-17
8.3.6.4
Slave ID .........................................................................................................8-17
8.3.6.5
Issuing EOI Commands in a Cascaded System ............................................8-17
8.3.6.6
Spurious Interrupts in a Cascaded System ...................................................8-18
8.3.7
Alternate Modes of Operation: Special Mask Mode ................................................8-19
8.3.8
Alternate Modes of Operation: Special Fully Nested Mode ....................................8-19
8.3.9
Alternate Modes of Operation: The Poll Command ................................................8-20
8.4
PROGRAMMING THE 8259A MODULE ..................................................................... 8-20
8.4.1
Initialization and Operation Command Words .........................................................8-20
8.4.2
Programming Sequence and Register Addressing .................................................8-21
8.4.3
Initializing the 8259A Module ..................................................................................8-21
8.4.3.1
8259A Initialization Sequence .......................................................................8-21
8.4.3.2
ICW1: Edge/Level Mode, Single/Cascade Mode ..........................................8-23
8.4.3.3
ICW2: Base Interrupt Type ............................................................................8-25
8.4.3.4
ICW3: Cascaded Pins/Slave Address ...........................................................8-26
8.4.3.5
ICW4: Special Fully Nested Mode, EOI Mode, Factory Test Modes .............8-26
8.4.4
The Operation Command Words ............................................................................8-30
8.4.4.1
Masking Interrupts: OCW1 ............................................................................8-30
8.4.4.2
EOI And Interrupt Priority: OCW2 .................................................................8-30
8.4.4.3
Special Mask Mode, Poll Mode and Register Reading: OCW3 .....................8-34
8.5
MODULE INTEGRATION: THE 80C186EC INTERRUPT CONTROL UNIT............... 8-36
8.5.1
Internal Interrupt Sources .......................................................................................8-36
8.5.1.1
Directly Supported Internal Interrupt Sources ...............................................8-37
8.5.1.2
Indirectly Supported Internal Interrupt Sources .............................................8-38
8.5.1.3
Using the Interrupt Request Latch Registers ................................................8-39
8.5.1.4
Using the Interrupt Request Latch Registers to Debug Interrupt Handlers ...8-40
8.6
HARDWARE CONSIDERATIONS WITH THE INTERRUPT CONTROL UNIT........... 8-42
8.6.1
Interrupt Latency and Response Time ....................................................................8-43
8.6.2
Resetting the Edge Detector ...................................................................................8-43
8.6.3
Ready Generation ...................................................................................................8-44
8.6.4
Connecting External 8259A Devices ......................................................................8-44
8.6.4.1
The External INTA Cycle ...............................................................................8-45
8.6.4.2
Timing Constraints ........................................................................................8-46
8.7
MODULE EXAMPLES ................................................................................................. 8-47
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