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CLOCK GENERATION AND POWER MANAGEMENT
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
IDLE
Idle Mode
PWRDN
Powerdown
Mode
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
5-12
Power Control Register
PWRCON
Arms power management functions.
Reset
Bit Name
State
0
Setting the IDLE bit forces the CPU to enter the
Idle mode when the HLT instruction is executed.
The PWRDN bit must be cleared when setting
the IDLE bit, otherwise Idle mode is not armed.
0
Setting the PWRDN bit forces the CPU to enter
the Powerdown mode when the next HLT
instruction is executed. The IDLE bit must be
cleared when setting the PWRDN bit, otherwise
Powerdown mode is not armed.
Figure 5-9. Power Control Register
0
I
P
D
W
L
R
E
D
N
A1129-0A
Function
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