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10.1.1.1
DMA Transfer Directions
The source and destination addresses for a DMA transfer are programmable and can be in either
memory or I/O space. DMA transfers can be programmed for any of the following four direc-
tions:
•
from memory space to I/O space
•
from I/O space to memory space
•
from memory space to memory space
•
from I/O space to I/O space
DMA transfers can access the Peripheral Control Block.
10.1.1.2
Byte and Word Transfers
DMA transfers can be programmed to handle either byte or word transfers. The handling of byte
and word data is the same as that for normal bus cycles and is dependent upon the processor bus
width. For example, odd-aligned word DMA transfers on a processor with a 16-bit bus requires
two fetches and two deposits (all back-to-back). BIU bus cycles are covered in Chapter 3, "Bus
Interface Unit." Word transfers are illegal on the 8-bit bus device.
10.1.2 Source and Destination Pointers
Each DMA channel maintains a twenty-bit pointer for the source of data and a twenty-bit pointer
for the destination of data. The twenty-bit pointers allow access to the full 1 Mbyte of memory
space. The DMA Unit views memory as a linear (unsegmented) array.
With a twenty-bit pointer, it is possible to create an I/O address that is above the CPU limit of 64
Kbytes. The DMA Unit will run I/O DMA cycles above 64K, even though these addresses are
not accessible through CPU instructions (e.g., IN and OUT). Some applications may wish to
make use of this by swapping pages of data from I/O space above 64K to standard CPU memory.
The source and destination pointers can be individually programmed to increment, decrement or
remain constant after each transfer. The programmed data width (byte or word) determines the
amount that a pointer is incremented or decremented. Word transfers change the pointer by two;
byte transfers change the pointer by one.
10.1.3 DMA Requests
There are three distinct sources of DMA requests: the external DRQ pin, the internal DMA re-
quest line and the system software. In all three cases, the system software must arm a DMA chan-
nel before it recognizes DMA requests. (See "Arming the DMA Channel" on page 10-23.)
DIRECT MEMORY ACCESS UNIT
10-3
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