Intel 80C188EC User Manual page 59

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Iteration control instructions can be used to regulate the repetition of software loops. These in-
structions use the CX register as a counter. Like the conditional transfers, the iteration control in-
structions are self-relative and can transfer only to targets that are within –128 to +127 bytes of
themselves. They are SHORT transfers.
The interrupt instructions allow programs and external hardware devices to activate interrupt ser-
vice routines. The effect of a software interrupt is similar to that of a hardware-initiated interrupt.
The processor cannot execute an interrupt acknowledge bus cycle if the interrupt originates in
software or with an NMI (Non-Maskable Interrupt).
Table 2-10. Interpretation of Conditional Transfers
Mnemonic
JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
NOTE: The terms above and below refer to the relationship of two unsigned values;
greater and less refer to the relationship of two signed values.
2-26
Condition Tested
(CF or ZF)=0
CF=0
CF=1
(CF or ZF)=1
CF=1
ZF=1
((SF xor OF) or ZF)=0
(SF xor OF)=0
(SF xor OF)=1
((SF xor OF) or ZF)=1
CF=0
ZF=0
OF=0
PF=0
SF=0
OF=1
PF=1
SF=1
"Jump if..."
above/not below nor equal
above or equal/not below
below/not above nor equal
below or equal/not above
carry
equal/zero
greater/not less nor equal
greater or equal/not less
less/not greater nor equal
less or equal/not greater
not carry
not equal/not zero
not overflow
not parity/parity odd
not sign
overflow
parity/parity equal
sign