Interrupt And Exception Priority - Intel 80C188EC User Manual

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
First Instruction Fetch
From Interrupt Routine
2.3.5

Interrupt and Exception Priority

Interrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable in-
terrupt are both recognized on the same instruction boundary, NMI has precedence. The
maskable interrupt will not be recognized until the Interrupt Enable bit is set and it is the highest
priority.
Only the single step exception can occur concurrently with another exception. At most, two ex-
ceptions can occur at the same instruction boundary and one of those exceptions must be the sin-
gle step. Single step is a special case; it is discussed on page 2-47. Ignoring single step (for now),
only one exception can occur at any given instruction boundary.
An exception has priority over both NMI and the maskable interrupt. However, a pending NMI
can interrupt the CPU at any valid instruction boundary. Therefore, NMI can interrupt an excep-
tion service routine. If an exception and NMI occur simultaneously, the exception vector is taken,
then is followed immediately by the NMI vector (see Figure 2-28). While the exception has high-
er priority at the instruction boundary, the NMI interrupt service routine is executed first.
2-46
Idle
Read IP
Idle
Read CS
Idle
Push Flags
Idle
Push CS
Push IP
Idle
Figure 2-27. Interrupt Response Factors
Clocks
5
4
5
4
4
4
3
4
4
5
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