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CLKOUT
READY
In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met.
1.
T
: READY low to clock high
CHIS
2.
T
: READY hold from clock high
CHIH
CLKOUT
READY
Alternatively, in a Normally-Ready system, a wait state will be inserted when1 & 2 are met.
1.
T
: READY low to clock low
CLIS
2.
T
: READY hold from clock low
CLIH
Failure to meet READY setup and hold can cause a device failure
!
(i.e., the bus hangs or operates inappropriately).
Conditions causing the BIU to become idle include the following.
•
The instruction prefetch queue is full.
•
An effective address calculation is in progress.
•
The bus cycle inherently requires idle states (e.g., interrupt acknowledge, locked opera-
tions).
•
Instruction execution forces idle states (e.g., HLT, WAIT).
T2
2
1
T2
1
Figure 3-18. Normally Ready System Timings
T3
TW
T3
TW
2
BUS INTERFACE UNIT
T4
T4
A1083-0A
3-19
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