Memory Support - Intel 6 Series User Manual

UNCOREPWRGOOD: Input from the chipset indicating that the system rails and
•
clocks are stable. Once the PWRGOOD is asserted, the processor is ready to be
brought out of reset.
PLT_RST#: The chipset asserts PLT_RST# signal during power-up or when
•
software initiates hardware reset to reset all the devices on the platform.
Some other key signals from processor are:
VCCSA_VID: VID output from processor to system agent VR. This input is used
•
by system agent VR to select the output voltage.
VCCP_SEL: VCCP_SEL pin of the processor (ball# A19) is used to select VCCP
•
voltage.
3.1.4

Memory Support

The development board supports dual-channel DDR3 memory interface with one
SODIMM per channel. The integrated memory controller can support a maximum of
two ranks of memory per channel.
There are two DDR3 SO-DIMM sockets (J4U1 for Channel A and J4V1 for Channel
B SODIMM slot) on the bottom side of board in stacked manner. Please see
for snapshots on stacked SODIMM slots.
The board supports:
• Data transfer rate: 1067 MT/s (PC3-8500), 1333MT/s (PC3-10600)
DDR3 SO-DIMM Modules supported:
•
o
o
o
o
• DDR3 DRAM device technology supported:
o
• DDR3 module with inbuilt thermal sensor can be supported. There is also an on-
board a thermal sensor (U2W2) closer to the SODIMMs.
2 nd Generation Intel ® Core™ Processor with Intel
User Guide
26
Raw Card A – double-sided, x16 data width, unbuffered, non-ECC
Raw Card B – single-sided, x8 data width, unbuffered, non-ECC
Raw Card C – single-sided, x16 data width, unbuffered, non-ECC
Raw Card F – double-sided, x8 data width, unbuffered, non-ECC
Standard 1-Gb, 2-Gb and 4-Gb technologies
® 6 Series Chipset Development Kit
Development Kit Features
Figure 2
March 2011
Document Number: 325208-001