Sharp MX-4100N Service Manual page 374

E. LSU PWB
Thermistor output
Reset input
JOBEND_INT
PCU
3
Clock synchronous serial communication
Print trigger input
Oscillator
(System CK)
ECLK
HSYNC
4
VSYNC
Image transfer CK
HSYNC
35:5
35:5
MFP
Clock synchronous serial communication
35:5
35:5
AMP
Hardware reset
Reset IC
ASIC
CHIP-2
Interruption output
ASIC
PCU I/F
CHIP-2
Register etc...
SCK
RSV_DAT
TRANS_RST
ASIC
CHIP-2
TRANS_DAT
ASIC
CHIP-2
PCU_TRG
SYSCLK
S/S
ASIC
CHIP-2
ECLK
HSYNC
VSYNC_M/Y
ASIC
VSYNC_K/C
Main Scan/
CHIP-2
Sub scan
timing control
ECKL
HSYNC
ASIC
CHIP-2
8
8
VIDEOIF_ACT
Print trigger chain
Hardware reset
Interruption output
PCU I/F
Register etc...
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
System CK
VSYNC_K/C
Main Scan/
ECLK
Sub scan
timing control
HSYNC
8
8
MX-5001N ELECTRICAL SECTION 10 – 7
TH
ID[0:0]
I2C BUS
Motor control
PGM_CK
PGM_START
(PGM_BREAK)
Polygon
PGM_LOCK
control
FAN_PWM
FAN control
FANSTABLE
CLK_C_EN
CLK_M_EN
CLK_A_EN
LSU_ASIC
CHIP-1
3
Serial transfer
DA_CLK
LD control
DA_DT
Serial DA_LD
D/A I/F
nSHMY x2
LD_ENB MY
LD control
(APC etc...)
nSHB MY x2
Channel A: M1 circuit
Channel B: M2 circuit
Channel C: Y1 circuit
Channel D: Y2 circuit
OSCCLK_C
OSCCLK_M
OSCCLK_A
ID[0:1]
I2C bus
Motor control
Polygon
Reserve circuit for LDD made by AKM
control
AKM_SDCLK
FAN control
nSHB MY x2
nSHB KC x2
AKM_RESET_LDD
LSU_ASIC
CHIP-2
AKM_CS_CMYK
AKM LDD serial communication
LD control
AKM_SCK
AKM_SDT
Serial
D/A I/F
nSH KC x2
LD_ENB KC
LD control
(APC etc...)
BD
nSHB KC x2
Channel A: K1 circuit
Channel B: K2 circuit
Channel C: C1 circuit
Channel D: C2 circuit
Thermistor
I2C
ROM
3
Polygon
O.C.
motor
LSU
O.C. O.C.
FAN
PIC
Vref YMCK x2
Serial 8
D/A
4
2
O.C.
LD5V
LDERR YMCK
BD
ASIC
CHIP-2
LD_CHK 1/2/3/4 4
DT_M1+- 2
DT_M2+- 2
DT_Y1+- 2
DT_Y2+- 2
CLK_C_EN
Oscillator
(Color CK)
CLK_M_EN
Oscillator
(Monochrome CK)
Oscillator CLK_A_EN
(Heavy paper CK)
LD
BD
I2C
ROM
AKM_APCSEL_CMYK
4
4
2
4
2
O.C.
LD5V
DT_K1+- 2
DT_K2+- 2
DT_C1+- 2
DT_C2+- 2