Memory Timing - Sun Microsystems Sun Blade 1000 Service Manual

Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
FIGURE C-5
C.1.3.6

Memory Timing

The CPU module memory controller is programmable so that different SDRAM
speeds can be accommodated at different system clock frequencies and different
processor clock ratios. The memory bus timing is controlled by a set of four memory
timing control registers.
C-16 Sun Blade 1000 and Sun Blade 2000 Service Manual • January 2002
Group 0 Group 1
Bank 2 Bank 1
Group 0 Group 1
Bank 2 Bank 1
Group 0 Group 1
Bank 2 Bank 1
Group 0 Group 1
Bank 2 Bank 1
Group 0 Group 1
Bank 2 Bank 1
Group 0 Group 1
Bank 2 Bank 1
One, Two, and Four Way Interleaving
1-way interleaving
Bank 3
1-way interleaving
Bank 3
Bank 3
2-way interleaving
Bank 3
2-way interleaving
Bank 3
2-way interleaving
Bank 3
4-way interleaving