Lan Design Considerations And Guidelines; Soc/Phy Interface Connections - Intel Quark SoC X1000 Design Manual

LAN Design Considerations and Guidelines—Intel
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LAN Design Considerations and Guidelines

The Intel
that can be used with an external PHY shown in
enable the component to process high-level commands and perform multiple
operations, which lowers processor use by off loading communication tasks from the
processor.
The SoC, which hereinafter refers to the integrated MAC within the SoC, supports an
MDIO interface for manageability. The integrated MAC supports multi-speed operation
(10/100 Mbps). The integrated MAC also operates in full-duplex at all supported speeds
or half-duplex at 10/100 Mbps as well as adhering to the IEEE 802.3x Flow Control
Specification.
Figure 90.

SOC/PHY Interface Connections

Note: The following sections are based on the TI DP83848I Port 10/100 Mb/s Ethernet PHY.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
®
Quark™ SoC X1000 incorporates an integrated 10/100 Mbps MAC controller
S o C
Figure 90. Its bus master capabilities
M D IO _ 0
M A C 0
R M II_ 0
M D IO _ 1
M A C 1
R M II_ 1
P H Y 0
P H Y 1
®
Intel Quark™ SoC X1000
PDG
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