GE Vivid S5 N Service Manual page 342

P R E L I M I N A R Y
GE
P N FN091065, R
ART UMBER
Section 5-4 Back End Processor
For reference, a list of abbreviations used in this section is provided in
Definitions" on page
Table 5-10
Abbreviation
BGA
CS
EMC
FPGA
HDD
MTBF
PCI
PLD
PIB
PMC
PS
PSB
5-4-2 ETX SBC Central Processing Unit (CPU)
The ETX SBC Central Processing Unit (CPU), which is mounted on top of the ETX Base Board (see
5-4-3 "ETX Base Board" on page
operations. In addition, the CPU supports the Front End via the PCI bus.
The CPU utilized in the Vivid™ S5 N and Vivid™ S6 N ultrasound unit is a Pentium -M, 1.4 GHz
Processor.
5-24
2
EVISION
5-24.
Abbreviations and Definitions
Ball Grid Array
Component Side
Electro Magnetic Compatibility
Field Programmable Gate Array
Hard disk drive
Mean Time Between Failures
Peripheral Card Interconnect
Programmable Logic Device
Probe Interface Board
Power Management Controller
Power Supply
Probe Select Board
5-25), controls and processes the internal Back End Processor
Section 5-4 - Back End Processor
(cont'd)
Definition
VS5 N VS6 N
S
AND
ERVICE
Table 5-10 "Abbreviations and
M
ANUAL