ST STM32L4 5 Series Reference Manual page 1667

Advanced arm-based 32-bit mcus

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OTG_FS Receive status debug read/OTG status read and

pop registers (OTG_GRXSTSR/OTG_GRXSTSP)

Address offset for Read: 0x01C

Address offset for Pop: 0x020

Reset value: 0x0000 0000

A read to the Receive status debug read register returns the contents of the top of the

Receive FIFO. A read to the Receive status read and pop register additionally pops the top

data entry out of the Rx FIFO.

The receive status contents must be interpreted differently in host and device modes. The

core ignores the receive status pop/read when the receive FIFO is empty and returns a

value of 0x0000 0000. The application must only pop the Receive Status FIFO when the

Receive FIFO non-empty bit of the Core interrupt register (RXFLVL bit in OTG_GINTSTS) is

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:17 PKTSTS: Packet status

Bits 16:15 DPID: Data PID

Bits 14:4 BCNT: Byte count

Bits 3:0 CHNUM: Channel number

Indicates the status of the received packet

0010: IN data packet received

0011: IN transfer completed (triggers an interrupt)

0101: Data toggle error (triggers an interrupt)

0111: Channel halted (triggers an interrupt)

Others: Reserved

Indicates the Data PID of the received packet

Indicates the byte count of the received IN data packet.

Indicates the channel number to which the current received packet belongs.

DocID024597 Rev 5

USB on-the-go full-speed (OTG_FS)

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