Hitachi H8/329 Series Hardware Manual page 149

(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
3
compare-match signal is inhibited.
Figure 6-20 shows this type of contention.
Ø
Internal address bus
Internal write signal
FRC
OCRA or OCRB
Compare-match
A or B signal
Figure 6-20. Contention between OCR Write and Compare-Match
Write cycle: CPU write to lower byte of OCRA or OCRB
T T
1 2
OCR address
N
N
140
T
3
N + 1
M
Write data
Inhibited