Hitachi H8/329 Series Hardware Manual page 65

Ø
Address bus
AS: High
RD: High
WR: High
Data bus: high impedance state
Figure 3-16. Pin States during On-Chip Register Field Access Cycle
Ø
Address bus
AS
RD
WR: High
Data bus
Figure 3-17 (a). External Device Access Timing (Read)
Bus cycle
T1 state T2 state
Address
Read cycle
T1 state T2 state
Address
Read data
56
T3 state
T3 state