Hitachi H8/329 Series Hardware Manual page 322

SSR—Serial Status Register
Bit 7
TDRE
Initial value 1
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Framing Error
0 Cleared when CPU reads FER = "1," then writes "0" in FER.
1 Set when a framing error occurs (stop bit is "0").
Overrun Error
0 Cleared when CPU reads ORER = "1," then writes "0" in ORER.
1 Set when an overrun error occurs (next data is completely received while
RDRF bit is set to "1").
Receive Data Register Full
0 Cleared when CPU reads RDRF = "1," then writes "0" in RDRF.
1 Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = "1," then writes "0" in TDRE
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = "0."
Note: * Software can write a "0" in bits 7 to 3 to clear the flags, but cannot write a "1" in these bits.
6 5
RDRF ORER FER
0 0
Multiprocessor Bit
0 Multiprocessor bit = "0" in receive data.
1 Multiprocessor bit = "1" in receive data.
Transmit End
0 Cleared when CPU reads TDRE = "1," then writes "0" in TDRE.
1 Set to "1" when TE = "0," or when TDRE = "1" at the end of
character transmission.
Parity Error
0 Cleared when CPU reads PER = "1," then writes "0" in PER.
1 Set when a parity error occurs (parity of receive data does not match
parity selected by O/E bit in SMR).
H'FFDC
4 3 2
PER TEND
0 0 0
R
Multiprocessor Bit Transfer
0 Multiprocessor bit = "0" in transmit data.
1 Multiprocessor bit = "1" in transmit data.
313
SCI
1 0
MPB MPBT
0 0
R R/W