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Internal address
bus
Internal write
signal
Compare-match
A or B signal
Figure 7-13. Contention between TCOR Write and Compare-Match
(4) Contention between Compare-Match A and Compare-Match B: If identical time constants
are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any
conflict between the output selections for compare-match A and B is resolved by following the
priority order in table 7-4.
Table 7-4. Priority of Timer Output
Output selection
Toggle
"1" Output
"0" Output
No change
Write cycle: CPU writes to TCORA or TCORB
Ø
TCNT
TCORA or
TCORB
Priority
High
Low
T
T
T
1
2
3
TCOR address
N
N
TCOR write data
160
N + 1
M
Inhibited
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