Hitachi H8/329 Series Hardware Manual page 63

Ø
Internal address bus
Internal Read signal
Internal data bus (read)
Internal Write signal
Internal data bus (write)
Figure 3-13. On-Chip Memory Access Cycle
Ø
Address bus
AS: High
RD: High
WR: High
Data bus: high impedance state
Figure 3-14. Pin States during On-Chip Memory Access Cycle
Bus cycle
T2 state
T1 state
Address
Read data
Write data
Bus cycle
T1 state
Address
54
T2 state