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Port 4 Data Direction Register (P4DDR)—H'FFB5
Bit
7
P4
DDR P4
7
Modes 1 and 2
Initial value
0
Read/Write
W
Mode 3
Initial value
0
Read/Write
W
P4DDR is an 8-bit register that selects the direction of each pin in port 4. A pin functions as an
output pin if the corresponding bit in P4DDR is set to "1," and as in input pin if the bit is cleared to
"0."
Port 4 Data Register (P4DR)—H'FFB7
Bit
7
P4
7
Initial value
0
Read/Write
R/W
Note: * Determined by the level at pin P4
P4DR is an 8-bit register containing the data for pins P4
output pins (P4DDR = "1") it reads the value in the P4DR latch, but for input pins (P4DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P4DR latch. This also applies to pins
used for interrupt input, A/D trigger input, clock output, and control signal input or output.
Pins P4
, P4
, and P4
0
1
2
or A/D trigger input. See table 5-11. If a pin is used for interrupt or A/D trigger input, its data
direction bit should be cleared to "0," so that the output from P4DR will not generate an interrupt
request or A/D trigger signal.
Pins P4
, P4
and P4
3
4
5
the RD, WR, and AS bus control signals. They are unaffected by the values in P4DDR and P4DR.
6
5
DDR P4
DDR P4
6
5
1
0
—
W
0
0
W
W
6
5
P4
P4
6
5
*
0
R
R/W
.
6
: Can be used for general-purpose input or output, interrupt request input,
: In modes 1 and 2 (the expanded modes), these pins are used for output of
4
3
2
DDR P4
DDR P4
DDR P4
4
3
2
0
0
0
W
W
W
0
0
0
W
W
W
4
3
2
P4
P4
P4
4
3
0
0
0
R/W
R/W
R/W
to P4
. When the CPU reads P4DR, for
7
0
89
1
0
DDR P4
DDR
1
0
0
0
W
W
0
0
W
W
1
0
P4
P4
2
1
0
0
0
R/W
R/W
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