Addressing Modes; Addressing Mode - Hitachi H8/329 Series Hardware Manual

3.3 Addressing Modes

3.3.1 Addressing Mode

The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these
addressing modes.
Table 3-1. Addressing Modes
No. Addressing mode
(1) Register direct
(2) Register indirect
(3) Register indirect with displacement
(4) Register indirect with post-increment
Register indirect with pre-decrement
(5) Absolute address
(6) Immediate
(7) Program-counter-relative
(8) Memory indirect
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV
instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)
which is added to the contents of the specified general register to obtain the operand address. For
the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment is
Symbol
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8
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