Hitachi H8/329 Series Hardware Manual page 312

Single-chip microcomputer
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MDCR—Mode Control Register
Bit
7
Initial value
1
Read/Write
Note: * Determined by inputs at pins MD
ISCR—IRQ Sense Control Register
Bit
7
Initial value
1
Read/Write
IER—IRQ Enable Register
Bit
7
Initial value
1
Read/Write
6
5
4
1
1
0
and MD
1
6
5
4
1
1
1
6
5
4
1
1
1
IRQ
to IRQ
0
0 IRQ
1 IRQ
303
H'FFC5
System Control
3
2
0
1
Mode Select Bits
Value at mode pins.
.
0
H'FFC6
System Control
3
2
IRQ
SC IRQ
2
1
0
R/W
IRQ
to IRQ
0
0 IRQ
is level-sensed (active Low).
i
1 IRQ
is edge-sensed (falling edge).
i
H'FFC7
System Control
3
2
IRQ
E
2
1
0
R/W
Enable
2
is disabled.
i
is enabled.
i
1
0
MDS1
MDS0
*
*
R
R
1
0
SC IRQ
SC
1
0
0
0
R/W
R/W
Sense Control
2
1
0
IRQ
E
IRQ
E
1
0
0
0
R/W
R/W

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