Section 12. Power-Down State; Overview - Hitachi H8/329 Series Hardware Manual

12.1 Overview

The H8/329 Series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 12-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 12-1. Power-Down State
Entering
Mode procedure
Sleep Execute
mode SLEEP
instruction
Soft- Set SSBY bit
ware in SYSCR to
standby "1," then
mode execute SLEEP
instruction
Hard- Set STBY
ware pin to Low
standby level
mode
Notes: 1. SYSCR: System control register
2. SSBY: Software standby bit

Section 12. Power-Down State

CPU
Clock CPU Reg's. Mod.
Run Halt Held
Halt Halt Held
Halt Halt Not
held
Sup.
RAM
Run Held
Halt Held
and
initial-
ized
Halt Held
and
initialized
239
I/O Exiting
ports methods
Held • Interrupt
• RES
• STBY
Held • NMI
• IRQ – IRQ
0
• STBY
• RES
High • STBY High,
impe- then RES
Low → High
dance
state
2