Hitachi H8/329 Series Hardware Manual page 185

Bit 2—Transmit End (TEND): This bit indicates that transmission of a character has ended and
the serial communication interface has stopped transmitting because there is no valid data in the
TDR. The TEND bit is also set to "1" when the TE bit in the serial control register (SCR) is
cleared to "0."
The TEND bit can be read but not written. To use the TEI interrupt, after TEND is cleared to "0"
at the start of data transmission, set TEIE to "1" to enable the interrupt.
Bit 2
TEND Description
0 To clear TEND, the CPU must read TDRE after
it has been set to "1," then write a "0" in TDRE.
1 This bit is set to "1" when:
(1) TE = "0"
(2) TDRE = "1" at the end of transmission of a character
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a
multiprocessor format in asynchronous communication mode. In synchronous mode, when a
multiprocessor format is not used, or if the RE bit is cleared to "0" when a multiprocessor format is
used, the MPB bit retains its previous value.
MPB can be read but not written.
Bit 1
MPB Description
0 Multiprocessor bit = "0" in receive data.
1 Multiprocessor bit = "1" in receive data.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted
in transmit data when a multiprocessor format is used in asynchronous communication mode. The
MPBT bit is double-buffered, in the same way that TSR and TDR are double-buffered. The MPBT
bit has no effect in synchronous mode, or when a multiprocessor format is not used.
Bit 0
MPBT Description
0 Multiprocessor bit = "0" in transmit data.
1 Multiprocessor bit = "1" in transmit data.
176
(Initial value)
(Initial value)
(Initial value)