Hitachi H8/329 Series Hardware Manual page 143

Ø
Input at FTI pin
Internal input
capture signal
If the upper byte of ICRx is being read when the input capture signal arrives, the internal input
capture signal is delayed by one state. Figure 6-12 shows the timing for this case.
Ø
Input at FTI pin
Internal input
capture signal
In buffer mode, this delay occurs if the CPU is reading either of the two registers concerned. When
ICRA and ICRC are used in buffer mode, for example, if the upper byte of either ICRA or ICRC is
being read when the FTIA input arrives, the internal input capture signal is delayed by one state.
Figure 6-13 shows the timing for this case. The case of ICRB and ICRD is similar.
Read cycle: CPU reads upper byte of ICRA or ICRC
Ø
Input at
FTIA pin
Internal input
capture signal
Figure 6-13. Input Capture Timing (1-State Delay, Buffer Mode)
Figure 6-11. Input Capture Timing (Usual Case)
Figure 6-12. Input Capture Timing (1-State Delay)
T T T
1 2 3
Read cycle: CPU reads upper byte of ICR
T T
1
134
T
2 3