Hitachi H8/329 Series Hardware Manual page 77

The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding
enable bits. When the enable bit is cleared to "0," the interrupt signal is not sent to the interrupt
controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU's
interrupt mask bit (I) to "1." Accordingly, these interrupts are accepted only when their enable bit
is set to "1" and the I bit is cleared to "0."
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware
standby mode.
When an NMI or another enabled interrupt is requested, the interrupt controller transfers the
interrupt request to the CPU and indicates the corresponding vector number. (When two or more
interrupts are requested, the interrupt controller selects the vector number of the interrupt with the
highest priority.) When notified of an interrupt request, at the end of the current instruction or
current hardware exception-handling sequence, the CPU starts the hardware exception-handling
sequence for the interrupt and latches the vector number.
Figure 4-4 is a flowchart of the interrupt (and reset) operations. Figure 4-6 shows the interrupt
timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM
and the stack is in on-chip RAM.
(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when
an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the
enable bit of that interrupt is set to "1."
(2) The interrupt controller checks the I bit in the CCR and accepts the interrupt request if the I bit
is cleared to "0." If the I bit is set to "1" only NMI requests are accepted; other interrupt
requests remain pending.
(3) Among all accepted interrupt requests, the interrupt controller selects the request with the
highest priority and passes it to the CPU. Other interrupt requests remain pending.
(4) When it receives the interrupt request, the CPU waits until completion of the current instruction
or hardware exception-handling sequence, then starts the hardware exception-handling
sequence for the interrupt and latches the interrupt vector number.
(5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the
stack. See figure 4-5. The stacked PC indicates the address of the first instruction that will be
executed on return from the software interrupt-handling routine.
(6) Next the I bit in the CCR is set to "1," masking all further interrupts except NMI.
(7) The vector address corresponding to the vector number is generated, the vector table entry at
this vector address is loaded into the program counter, and execution branches to the software
interrupt-handling routine at the address indicated by that entry.
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