Hitachi H8/329 Series Hardware Manual page 6

7.3.3 External Reset of TCNT .......................................................................................... 155
7.3.4 Setting of TCSR Overflow Flag (OVF) .................................................................. 156
7.4 Interrupts............................................................................................................................... 157
7.5 Sample Application............................................................................................................... 157
7.6 Application Notes ................................................................................................................. 158
Section 8. Serial Communication Interface
8.1 Overview............................................................................................................................... 163
8.1.1 Features.................................................................................................................... 163
8.1.2 Block Diagram......................................................................................................... 164
8.1.3 Input and Output Pins .............................................................................................. 164
8.1.4 Register Configuration ............................................................................................ 165
8.2 Register Descriptions............................................................................................................ 166
8.2.1 Receive Shift Register (RSR) .................................................................................. 166
8.2.2 Receive Data Register (RDR)-H'FFDD................................................................ 166
8.2.3 Transmit Shift Register (TSR)................................................................................. 166
8.2.4 Transmit Data Register (TDR)-H'FFDB............................................................... 167
8.2.5 Serial Mode Register (SMR)-H'FFD8 .................................................................. 167
8.2.6 Serial Control Register (SCR)-H'FFDA ............................................................... 170
8.2.7 Serial Status Register (SSR)-H'FFDC .................................................................. 174
8.2.8 Bit Rate Register (BRR)-H'FFD9 ......................................................................... 177
8.2.9 Serial/Timer Control Register (STCR)-H'FFC3 ................................................... 181
8.3 Operation .............................................................................................................................. 182
8.3.1 Overview ................................................................................................................. 182
8.3.2 Asynchronous Mode................................................................................................ 184
8.3.3 Clocked Synchronous Operation ............................................................................. 197
8.4 SCI Interrupts........................................................................................................................ 206
8.5 Application Notes ................................................................................................................. 206
Section 9. A/D Converter
9.1 Overview............................................................................................................................... 209
9.1.1 Features.................................................................................................................... 209
9.1.2 Block Diagram......................................................................................................... 210
9.1.3 Input Pins................................................................................................................. 211
9.1.4 Register Configuration ............................................................................................ 211
9.2 Register Descriptions............................................................................................................ 212
9.2.1 A/D Data Registers (ADDR)-H'FFE0 to H'FFE6................................................. 212
9.2.2 A/D Control/Status Register (ADCSR)-H'FFE8 .................................................. 212
..................................................................... 163
..................................................................................................... 209
iv