Number Of States Required For Execution - Hitachi H8/329 Series Hardware Manual

A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I × S
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2,
From table A-3: S
I
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A-4: I = 2,
From table A-3: S
I
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution status
(instruction cycle)
Instruction fetch S
Branch address read S
Stack operation S
Byte data access S
Word data access S
Internal operation S
Note: m: Number of wait states inserted in access to external device.
+ J × S + K × S + L × S
I J K
J = K = M = N= 0
= 8, S = 3
L
J = K = 1, L = M = N = 0
= S = S = 8
J K
On-chip memory On-chip reg. field
I
J
2
K
L
M
N
+ M × S + N × S
L M N
Access location
6
3
6
1
280
External memory
6 + 2m
3 + m
6 + 2m