Hitachi H8/329 Series Hardware Manual page 156

Bit 7
CMIEB Description
0 Compare-match interrupt request B (CMIB) is disabled.
1 Compare-match interrupt request B (CMIB) is enabled.
Bit 6-Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
control/status register (TCSR) is set to "1".
Bit 6
CMIEA Description
0 Compare-match interrupt request A (CMIA) is disabled.
1 Compare-match interrupt request A (CMIA) is enabled.
Bit 5-Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR)
is set to "1".
Bit 5
OVIE Description
0 The timer overflow interrupt request (OVI) is disabled.
1 The timer overflow interrupt request (OVI) is enabled.
Bits 4 and 3-Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or Bor by an external reset input.
Bit 4 Bit 3
CCLR1 CCLR0
0 0
0 1
1 0
1 1
Description
Not cleared.
Cleared on compare-match A.
Cleared on compare-match B.
Cleared on rising edge of external reset input signal.
147
(Initial value)
(Initial value)
(Initial value)
(Initial value)