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Interrupt priority
decision. Wait for
end of instruction.
Interrupt request
signal
Ø
Internal address
bus
Internal Read
signal
Internal Write
signal
Internal 16-bit
data bus
(1)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
interrupt-handling routine.)
(1)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from
(2) (4)
Instruction code (Not executed)
interrupt-handling routine.)
(2) (4) Instruction code (Not executed)
(3)
Instruction prefetch address (Not executed)
(3)
Instruction prefetch address (Not executed)
(5)
SP–2
(5)
SP–2
(6)
SP–4
(6)
SP–4
(7)
CCR
(7)
CCR
(8)
Address of vector table entry
(8)
Address of vector table entry
(9)
Vector table entry (address of first instruction of interrupt-handling routine)
(9)
Vector table entry (address of first instruction interrupt-handling routine)
(10)
First instruction of interrupt-handling routine
(10)
First instruction of interrupt-handling routine
Interrupt
accepted
Instruction
Internal
fetch
process-
ing
(1)
(3)
(2)
(4)
Figure 4-6. Timing of Interrupt Sequence
Vector
Stack
fetch
(5)
(6)
(8)
(1)
(7)
(9)
71
Instruction fetch
(first instruction of
Internal
interrupt-handling
process-
routine)
ing
(9)
(10)
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