Hitachi H8/329 Series Hardware Manual page 144

Figure 6-14 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
Ø
FTIA
Internal input
capture signal
n
FRC
ICRA M
ICRC m
Figure 6-14. Buffered Input Capture with Both Edges Selected
In this mode, FTIC does not cause the FRC contents to be copied to ICRC. However, input capture
flag C still sets on the edge of FTIC selected by IEDGC, and if the interrupt enable bit (ICICE) is
set, a CPU interrupt is requested.
The situation when ICRB and ICRD are used in buffer mode is similar.
n + 1
n
M
135
N
n N
M n
N + 1