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SP-4
SP-3
SP-2
SP-1
SP(R7)
Stack area
Before interrupt
is accepted
PC:
Program counter
CCR:
Condition code register
SP:
Stack pointer
Notes:
1.
The PC contains the address of the first instruction
executed after return.
2.
Registers must be saved and restored by word
access at an even address.
* Ignored on return.
Figure 4-5. Usage of Stack in Interrupt Handling
SP(R7)
SP+1
SP+2
SP+3
SP+4
Pushed onto stack
70
CCR
CCR*
PC (upper byte)
PC (lower byte)
Even address
After interrupt
is accepted
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