Hitachi H8/329 Series Hardware Manual page 127

Note: * The FRC contents are transferred to the input capture register regardless of the value of
the input capture flag (ICFA/B/C/D).
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
the timer control register (TCR) is set to "1," ICRC is used as a buffer register for ICRA as shown
in figure 6-2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and
the new FRC count is copied into ICRA.
FTIA
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Similarly, when the BUFEB bit in TIER is set to "1," ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges of
the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge.
BUFEA
IEDGA IEDGC
Edge detect and
capture signal
generating circuit
ICRC
Buffer Enable A
Input Edge Select A
Input Edge Select C
Input Capture Register C
Input Capture Register A
Free-Running Counter
Figure 6-2. Input Capture Buffering
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FRC
ICRA