Hitachi H8/329 Series Hardware Manual page 198

In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to "0" the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to "1" and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) is set to "1" in SCR, the SCI requests
a TXI interrupt (TDR-empty interrupt) at this time.
Serial transmit data are transmitted in the following order from the TxD pin:
(a) Start bit: one "0" bit is output.
(b) Transmit data: seven or eight bits are output, LSB first.
(c) Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
(d) Stop bit: one or two "1" bits (stop bits) are output.
(e) Mark state: output of "1" bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is "0," the SCI loads new
data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame.
If TDRE is "1," the SCI sets the TEND bit to "1" in SSR, outputs the stop bit, then continues
output of "1" bits in the mark state. If the TEIE bit (TSR-empty interrupt enable) in SCR is set
to "1," a TEI interrupt (TSR-empty interrupt) is requested.
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