Hitachi H8/329 Series Hardware Manual page 194

Table 8-7. Data Formats in Asynchronous Mode
SMR Bits
CHR PE MP STOP
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
1 0 0 0
1 0 0 1
1 1 0
0
1 1 0 1
0 — 1 0
0 — 1 1
1 — 1 0
1 — 1 1
Notes: SMR: Serial mode register
START: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
(2) Clock: In asynchronous mode it is possible to select either an internal clock created by the on-
chip baud rate generator, or an external clock input at the SCK pin. The clock selection depends on
the C/A bit in the serial mode register (SMR) and the CKE0 and CKE1 bits in the serial control
register (SCR). Refer to table 8-6.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used
for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the
center of the transmit data bits. Figure 8-3 shows the phase relationship between the output clock
and transmit data.
1 2 3 4
S
S
S
S
S
S
S
S
S
S
S
S
185
5 6 7 8
8-Bit data
8-Bit data
8-Bit data
8-Bit data
7-Bit data
7-Bit data
7-Bit data
7-Bit data
8-Bit data
8-Bit data
7-Bit data
7-Bit data
9 10 11 12
STOP
STOP STOP
P STOP
P STOP STOP
STOP
STOP STOP
P STOP
P STOP STOP
MPB STOP
MPB STOP STOP
MPB STOP
MPB STOP STOP