Hitachi H8/329 Series Hardware Manual page 111

Port 6 Data Register (P6DR)—H'FFBB
Bit 7
P6
7
Initial value 0
Read/Write R/W
P6DR is an 8-bit register containing the data for pins P6
output pins (P6DDR = "1") it reads the value in the P6DR latch, but for input pins (P6DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P6DR latch. This also applies to pins
used for timer input and output.
Pin P6 : This pin can be used for general-purpose input or output, and input of external clock
0
signals to the 16-bit free-running timer and 8-bit timer 0. External clock input is selected by the
CKS bits of the timers. When this pin is used for timer clock input, its P6DDR bit should normally
be cleared to "0;" otherwise the timer will receive the value in P6DR.
Pin P6 : This pin can be used for general-purpose input or output, or for 16-bit free-running timer
1
output (FTOA). When timer output is selected by the OEA bit of the 16-bit free-running timer, this
pin is unaffected by the values in P6DDR and P6DR.
Pin P6 : This pin can be used for general-purpose input or output, and input of the FTIA input
2
capture signal to the 16-bit free-running timer. FTIA input can operate simultaneously with
general-purpose input or output.
Pin P6 : This pin can be used for general-purpose input or output, input of the FTIB input capture
3
signal to the 16-bit free-running timer, and input of the timer reset signal to 8-bit timer 0. FTIB
input operates simultaneously with the other functions. Reset signal input is selected by the CCLR
bits of 8-bit timer 0. When this pin is used for timer reset signal input, its P6DDR bit should
normally be cleared to "0;" otherwise the timer will receive the value in P6DR.
Pin P6 : This pin can be used for general-purpose input or output, input of the FTIC input capture
4
signal to the 16-bit free-running timer, or output from 8-bit timer 0. FTIC input operates
simultaneously with the other functions. When 8-bit timer output is selected by the OS bits of 8-bit
timer 0, this pin is unaffected by the values in P6DDR and P6DR.
6 5 4
P6 P6 P6
6 5
0 0 0
R/W R/W R/W
102
3 2
P6 P6
4 3 2
0 0
R/W R/W
to P6 . When the CPU reads P6DR, for
7 0
1 0
P6 P6
1 0
0 0
R/W R/W