Hitachi H8/329 Series Hardware Manual page 303

TCR—Timer Control Register
Bit 7
IEDGA IEDGB
Initial value 0
Read/Write R/W
Input Edge Select B
0 Falling edge of FTIB is valid.
1 Rising edge of FTIB is valid.
Input Edge Select A
0 Falling edge of FTIA is valid.
1 Rising edge of FTIA is valid.
6 5
IEDGC IEDGD BUFEA BUFEB
0 0
R/W R/W
Buffer Enable B
0 ICRD is used for input capture D.
1 ICRD is buffer register for input capture B.
Buffer Enable A
0 ICRC is used for input capture C.
1 ICRC is buffer register for input capture A.
Input Edge Select D
0 Falling edge of FTID is valid.
1 Rising edge of FTID is valid.
Input Edge Select C
0 Falling edge of FTIC is valid.
1 Rising edge of FTIC is valid.
H'FF96
4 3 2
0 0 0
R/W R/W R/W
Clock Select
0 0 Internal clock source: Ø/2
0 1 Internal clock source: Ø/8
1 0 Internal clock source: Ø/32
1 1 External clock source: counted on rising edge
294
FRT
1 0
CKS1 CKS0
0 0
R/W R/W