Hitachi H8/329 Series Hardware Manual page 311

STCR—Serial/Timer Control Register
Bit 7
—
Initial value 1
Read/Write —
SYSCR—System Control Register
Bit 7
SSBY
Initial value 0
Read/Write R/W
Software Standby
0 SLEEP instruction causes transition to sleep mode.
1 SLEEP instruction causes transition to software standby mode.
6 5
— —
1 1
— —
Multiprocessor Enable
0 Multiprocessor communication function is disabled.
1 Multiprocessor communication function is enabled.
6 5
STS2 STS1 STS0
0 0
R/W R/W R/W
NMI Edge
0 Falling edge of NMI is detected.
1 Rising edge of NMI is detected.
Standby Timer Select
0 0 0 Clock settling time = 8192 states
0 0 1 Clock settling time = 16384 states
0 1 0 Clock settling time = 32768 states
0 1 1 Clock settling time = 65536 states
1 – – Clock settling time = 131072 states
H'FFC3
4 3 2
— — MPE
1 1 0
— — R/W
Internal Clock Source Select
See TCR under TMR0 and TMR1.
H'FFC4
4 3 2
— NMIEG
0 1 0
— R/W
RAM Enable
0 On-chip RAM is disabled.
1 On-chip RAM is enabled.
302
TMR0/1
1 0
ICKS1 ICKS0
0 0
R/W R/W
System Control
1 0
— RAME
1 1
— R/W