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Table 1-3. Pin Functions (2)
Type
Symbol
Data bus
D
to D
7
0
WAIT
Bus
control
RD
WR
AS
NMI
Interrupt
signals
IRQ
to
0
IRQ
2
Operating
MD
,
1
mode
MD
0
control
Pin No.
DC-64S
DP-64S FP-64A CP-68
57 to 64 49 to 56 61 to 68
8
64
9
4
60
5
5
61
6
6
62
7
13
5
14
1 to 3
57 to 59 2 to 4
19,
11,
21,
20
12
22
I/O Name and function
I/O Data bus: 8-Bit bidirectional data bus.
I
Wait: Requests the CPU to insert T
states into the bus cycle when an external
address is accessed.
O
Read: Goes Low to indicate that the CPU
is reading an external address.
O
Write: Goes Low to indicate that the CPU
is writing to an external address.
O
Address Strobe: Goes Low to indicate
that there is a valid address on the address
bus.
I
NonMaskable Interrupt: Highest-
priority interrupt request. The NMIEG bit
in the system control register (SYSCR)
determines whether the interrupt is
requested on the rising or falling edge of
the NMI input.
I
Interrupt Request 0 to 2: Maskable
interrupt request pins.
I
Mode: Input pins for setting the MCU
operating mode according to the table
below.
MD
MD
1
0
0
1
1
0
1
1
12
W
Mode
Description
Mode 1 Expanded mode
with on-chip ROM
disabled
Mode 2 Expanded mode
with on-chip ROM
enabled
Mode 3 Single-chip mode
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