Hitachi H8/329 Series Hardware Manual page 159

Bit 5—Timer Overflow Flag (OVF): This status flag is set to "1" when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 5
OVF Description
0 To clear OVF, the CPU must read OVF after
it has been set to "1," then write a "0" in this bit.
1 This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 4—Reserved: This bit cannot be modified and is always read as "1."
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match
events on the timer output signal (TCOR or TCNT). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
If compare-match A and B occur simultaneously, any conflict is resolved as explained in item (4) in
section 7.6, "Application Notes."
After a reset, the timer output is "0" until the first compare-match event.
When all four output select bits are cleared to "0" the timer output signal is disabled.
Bit 3 Bit 2
OS3 OS2
0 0
0 1
1 0
1 1
Bit 1 Bit 0
OS1 OS0
0 0
0 1
1 0
1 1
Description
No change when compare-match B occurs.
Output changes to "0" when compare-match B occurs.
Output changes to "1" when compare-match B occurs.
Output inverts (toggles) when compare-match B occurs.
Description
No change when compare-match A occurs.
Output changes to "0" when compare-match A occurs.
Output changes to "1" when compare-match A occurs.
Output inverts (toggles) when compare-match A occurs.
150
(Initial value)
(Initial value)
(Initial value)