Hitachi H8/329 Series Hardware Manual page 285

Single-chip microcomputer
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Table A-1. Instruction Set (cont.)
Mnemonic
BIOR #xx:3,@Rd
B
6
BIOR #xx:3, @aa:8
B
6
BXOR #xx:3,Rd
B
2
BXOR #xx:3,@Rd
B
6
BXOR #xx:3, @aa:8
B
6
BIXOR #xx:3,Rd
B
2
BIXOR #xx:3,@Rd
B
6
BIXOR #xx:3, @aa:8
B
6
BRA d:8 (BT d:8)
4
BRN d:8 (BF d:8)
4
BHI d:8
4
BLS d:8
4
BCC d:8 (BHS d:8)
4
BCS d:8 (BLO d:8)
4
BNE d:8
4
BEQ d:8
4
BVC d:8
4
BVS d:8
Operation
Branching
condition
C∨(#xx:3 of @Rd16) → C
C∨(#xx:3 of @aa:8) → C
C⊕(#xx:3 of Rd8) → C
C⊕(#xx:3 of @Rd16) → C
C⊕(#xx:3 of @aa:8) → C
C⊕(#xx:3 of Rd8) → C
C⊕(#xx:3 of @Rd16) → C
C⊕(#xx:3 of @aa:8) → C
PC ← PC+d:8
PC ← PC+2
C ∨ Z = 0
if condition
C ∨ Z = 1
is true then
PC ← PC+d:8
C = 0
else next;
C = 1
Z = 0
Z = 1
V = 0
276
V = 1
Addressing mode/
instruction length
Condition code
I
H N Z V C
4
4
2
4
4
2
4
4
2
2
2
2
2
2
2
2
2
2
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –

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