Cpu States - Hitachi H8/329 Series Hardware Manual

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Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5 →
R5 + R4L →
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
R5 + R4L →

3.6 CPU States

The CPU has three states: the program execution state, exception-handling state, and power-down
state. The power-down state is further divided into three modes: the sleep mode, software standby
mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a
map of the state transitions.
State Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes a hardware
sequence that includes loading the program counter from the vector table.
Power-down state
A state in which some or all of the chip
functions are stopped to conserve power.
8 7
Op
Op
← R6
← R6 + R4L
← R6
H'FFFF
← R6 + R4L
Not allowed
Figure 3-11. Operating States
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0
EEPROM
Op: Operation field
Sleep mode
Software standby mode
Hardware standby mode