Hitachi H8/329 Series Hardware Manual page 74

Bits 0 to 2—IRQ to IRQ
0
IRQ to IRQ are level-sensed or sensed on the falling edge.
0 2
Bits 0 to 2
IRQ SC to IRQ SC
0 2
0
1
IRQ Enable Register (IER)—H'FFC7
Bit 7
—
Initial value 1
Read/Write —
Bits 3 to 7—Reserved: These bits cannot be modified and are always read as "1."
Bits 0 to 2—IRQ to IRQ
0
IRQ interrupts individually.
2
Bits 0 to 2
IRQ E to IRQ E
0 2
0
1
When edge sensing is selected (by setting bits IRQ
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ
IRQ E) is cleared to "0" and the interrupt is disabled. If an interrupt is requested while the
7
enable bit (IRQ E to IRQ
0
enable bit is cleared to "0" while the request is still pending, the request will remain pending,
although new requests will not be recognized. If the interrupt mask bit (I) in the CCR is
cleared to "0," the interrupt-handling routine can be executed even though the enable bit is
now "0."
Sense Control (IRQ
2
Description
An interrupt is generated when IRQ
inputs are Low.
An interrupt is generated by the falling edge of the IRQ
6 5
— —
1 1
— —
Enable (IRQ E to IRQ
2 0
Description
IRQ to IRQ interrupt requests are disabled.
0 2
IRQ to IRQ interrupt requests are enabled.
0 2
E) is set to "1," the request will be held pending until served. If the
7
SC to IRQ SC): These bits determine whether
0 2
to IRQ
0 2
4 3 2
— — IRQ
1 1 0
— — R/W
E): These bits enable or disable the IRQ
2
SC to IRQ SC to "1"), it is possible for an
0 7
65
(Initial state)
to IRQ inputs.
0 2
1 0
E IRQ E IRQ E
2 1 0
0 0
R/W R/W
(Initial state)
E to
0
to
0